In computer architecture, a superscalar computer, i.e., a computer with multiple processing components that together may execute more than one instruction per clock cycle, may be used for computation-intensive applications. Often, superscalar computers will employ a central processing unit (CPU) that includes several execution resources, such as one or more function units, for executing multiple instructions simultaneously. Examples of a function unit may include an arithmetic logic unit, a bit shifter, or a multiplier. Executing multiple instructions with multiple function units simultaneously may allow faster overall CPU throughput than would otherwise be possible if instructions are executed one at a time with a single function unit.
With a CPU having multiple function units, each function unit may be associated with an instruction selection logic circuit that logically selects an instruction to be executed from a queue of instructions.
It may happen, however, that the selection logic for two different function units selects the same instruction for execution during the same cycle, i.e., at the same time. This situation is called an instruction collision, and may be wasteful of computational time and effort. Because multiple function units simultaneously executing a same instruction may cause a data error or another problem, the processor typically prohibits such simultaneous execution of an instruction. Therefore, when an instruction collision occurs, the processor selects one of the function units to execute the instruction, and causes all of the other function units that attempted to execute the instruction to instead execute a “no operation instruction” (NOP), which is effectively a wait state that typically serves no useful purpose.